This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-37349, filed on Feb. 14, 2002, the entire contents of which are incorporated herein by reference.
1) Field of the Invention
The present invention relates to a digital-analog converter (DAC) used in the analog integrated circuits or the analog-digital hybrid integrated circuits.
2) Description of the Related Art
A conventional resistance-division type DAC is shown in FIG. 1. This DAC includes resistors R0, R1, . . . , and Rj, and switches SW0, SW1, . . . , and SWj, where j is a natural number. The resistors R0, R1, . . . , and Rj are connected in series (resistor row). One terminal of each of the switches SW0, SW1, . . . , and SWj is connected to a node between two adjacent resistors and the other terminal is connected to one terminal of the first resistor R0. The other terminal of the first switch R0 is connected to ground potential. A power source applies a voltage VDD to one terminal of the last resistor Rj. The switches are ON/OFF controlled based on an input code, which is not shown, to obtain a resistance-divided voltage of the voltage VDD at an output terminal dout.
Sometimes more than one DAC""s are necessary in the integrated circuits. In that case, desired number of DAC""s having the structure shown in FIG. 1 can be used, or one DAC can be provided and the resistor row of that DAC can be shared to construct other DAC""s.
FIG. 2 shows a twofold DAC in which a resistor row of one DAC is shared by other DAC. This twofold DAC includes series connected resistors R0, R1, R2, . . . , Rj, switches SW01, SW11, SW21, . . . , SWj1, and SW02, SW12, SW22, . . . , SWj2. One terminal of each of the switches SW01 and SW02, SW11 and SW12, . . . , and SWj1 and SWj2, is connected to a node between two adjacent resistors and the other terminal is connected to one terminal of the first resistor R0. The rest of the structure of the twofold DAC is the same as that of the DAC shown in FIG. 1. The switches SW01, SW11, SW21, . . . , SWj1 are ON/OFF controlled based on a first input code, the switches SW02, SW12, SW22, . . . , SWj2 are ON/OFF controlled based on a second input code. As a result, first and second resistance-divided voltages of the voltage VDD are output from first and second output terminals dout1 and dout2 respectively. The first and the second input codes have not been shown in the diagram. A threefold DAC or even a multifold DAC can be constructed in a similar manner as the twofold DAC.
Consider that many DAC""s having the structure shown in FIG. 1 are used in the integrated circuit. In that case, since the DAC""s occupy a large area, the size of the integrated circuit will disadvantageously increase.
Now consider that a multifold DAC (e.g., a twofold DAC shown in FIG. 2) is used in the integrated circuit. In that case, the number of the switches becomes very large. For example, consider an m-fold resistance-division type DAC of n bits, where n and m are natural numbers. In this DAC, 2n resistors and mxc3x972n switches will be required. For the sake of convenience, the manner in which the resistors and the switches are connected in a multifold DAC will be called xe2x80x9csimple multifolding.xe2x80x9d
It is an object of this invention to provide a multifold DAC that can be realized with lesser switches.
According to a first aspect of the present invention, a multifold DAC has the following structure. When n is an even number, the multifold DAC has a resistor row that has 2n resistors connected in series. One switch is connected to the end terminal of this resistor row and to each node between adjacent resistors respectively. These 2n switches will be called a first switch group. Nodes x0 to x(2nxe2x88x921) that are not connected to the resistor row of the switches that are included in the first switch group, are short-circuited by 2n/2. The node group having the nodes short-circuited by 2n/2 will be called a first node group. Then, the first node group consists of 2n/2 nodes.
One more switch is also connected to the end terminal of the resistor row and to each node between adjacent resistors respectively. These 2n switches will be called a second switch group. Nodes y0 to y(2nxe2x88x921) that are not connected to the resistor row of the switches that are included in the second switch group, are also short-circuited by 2n/2. Regarding the nodes y0 to y(2nxe2x88x921), the node group having the nodes short-circuited by 2n/2 will be called a second node group. Then, the second node group also consists of 2n/2 nodes. Each node group included in the first node group and the second node group is connected to two to five different output terminals via mutually independent switches. The switches included in the first switch group and the second switch group are ON/OFF controlled according to a plurality of input codes such that each node group included in the first node group and the second node group is not connected to the resistor row at two or more positions.
In the first aspect, when n is an odd number, the first node group has the nodes x0 to x(2nxe2x88x921) short-circuited by 2(n+1)/2, and the first node group consists of 2(nxe2x88x921)/2 nodes. The second node group has the nodes y0 to y(2nxe2x88x921) short-circuited by 2(nxe2x88x921)/2, and the second node group consists of 2(n+1)/2 nodes.
According to the first aspect of the invention, it is possible to share one resistor row with the DACs by using a smaller number of switches than the number of DACs according to a simple multifolding.
According to a second aspect of the invention, a multifold DAC has the following structure. When n is an even number, the multifold DAC has a resistor row that has 2n resistors connected in series. One switch is connected to the end terminal of this resistor row and to each node between adjacent resistors respectively. These 2n switches will be called a first switch group. Nodes x0 to x(2nxe2x88x921) that are not connected to the resistor row of the switches that are included in the first switch group, are disposed in a matrix shape of 2n/2xc3x972n/2. A switch is connected between adjacent nodes. A plurality of switches provided between these nodes will be called a second switch group.
Nodes disposed corresponding to a first side of the outermost periphery among the node groups disposed in the matrix shape are connected to a first output terminal via mutually independent switches. Nodes disposed corresponding to a second side of the outermost periphery are connected to a second output terminal via mutually independent switches. Nodes disposed corresponding to a third side of the outermost periphery are connected to a third output terminal via mutually independent switches. Nodes disposed corresponding to a fourth side of the outermost periphery are connected to a fourth output terminal via mutually independent switches. The switches included in the second switch group are ON/OFF controlled according to a plurality of input codes such that a route short-circuited by the first output terminal, a route short-circuited by the second output terminal, a route short-circuited by the third output terminal, and a route short-circuited by the fourth output terminal are not mutually short-circuited.
In the second aspect, when n is an odd number, the nodes x0 to x(2nxe2x88x921) are disposed in a matrix shape of 2(n+1)/2xc3x972(nxe2x88x921)/2.
According to the second aspect, it is possible to share one resistor row with the DACs by using a smaller number of switches than the number of DACs according to a simple multifolding.